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k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c this is a family of 4,194,304 x 4 bit fast page mode cmos drams. fast page mode offers high speed random access of memory cells within the same row. power supply voltage (+5.0v or +3.3v), refresh cycle (2k ref. or 4k ref.), access time (-50 or -60), power con- sumption(normal or low power) and package type(soj or tsop-ii) are optional features of this family. all of this family have cas - before- ras refresh, ras -only refresh and hidden refresh capabilities. furthermore, self-refresh operation is available in l-version. this 4mx4 fast page mode dram family is fabricated using samsung s advanced cmos process to realize high band-width, low power consumption and high reliability. it may be used as main memory for high level computer, microcomputer and personal computer. ? part identification - k4f170411c-b(f) (5v, 4k ref.) - K4F160411C-B(f) (5v, 2k ref.) - k4f170412c-b(f) (3.3v, 4k ref.) - k4f160412c-b(f) (3.3v, 2k ref.) ? fast page mode operation ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? self-refresh capability (l-ver only) ? fast parallel test mode capability ? ttl(5v)/lvttl(3.3v) compatible inputs and outputs ? early write or output enable controlled write ? jedec standard pinout ? available in plastic soj and tsop(ii) packages ? single +5v 10% power supply (5v product) ? single +3.3v 0.3v power supply (3.3v product) control clocks ras cas w vcc vss dq0 to dq3 a0-a11 (a0 - a10) *1 a0 - a9 (a0 - a10) *1 memory array 4,194,304 x 4 cells samsung electronics co., ltd. reserves the right to change products and specifications without notice. 4m x 4bit cmos dynamic ram with fast page mode description features functional block diagram ? refresh cycles part no. v cc refresh cycle refresh period nor- l-ver k4f170411c 5v 4k 64ms 128ms k4f170412c 3.3v k4f160411c 5v 2k 32ms k4f160412c 3.3v ? performance range speed t rac t cac t rc t pc remark -50 50ns 13ns 90ns 35ns 5v/3.3v -60 60ns 15ns 110ns 40ns 5v/3.3v ? active power dissipation speed 3.3v 5v 4k 2k 4k 2k -50 324 396 495 605 -60 288 360 440 550 unit : mw s e n s e a m p s & i / o data out buffer data in buffer oe note) *1 : 2k refresh col. address buffer row address buffer refresh counter refresh control refresh timer column decoder row decoder vbb generator
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c v cc dq0 dq1 w ras *a11(n.c) a10 a0 a1 a2 a3 v cc v ss dq3 dq2 cas oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pin configuration (top views) pin name pin function a0 - a11 address inputs (4k product) a0 - a10 address inputs (2k product) dq0 - 3 data in/out v ss ground ras row address strobe cas column address strobe w read/write input oe data output enable v cc power(+5v) power(+3.3v) n.c no connection (2k ref. product) v cc dq0 dq1 w ras *a11(n.c) a10 a0 a1 a2 a3 v cc v ss dq3 dq2 cas oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 *a11 is n.c for k4f160411(2)c (5v/3.3v, 2k ref. product) b : 300mil 26(24) soj f : 300mil 26(24) tsop ii ? k4f17(6)0411(2)c-b ? k4f17(6)0411(2)c-f
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c absolute maximum ratings * permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. parameter symbol rating units 3.3v 5v voltage on any pin relative to v ss v in, v out -0.5 to +4.6 -1.0 to +7.0 v voltage on v cc supply relative to v ss v cc -0.5 to +4.6 -1.0 to +7.0 v storage temperature tstg -55 to +150 -55 to +150 c power dissipation p d 1 1 w short circuit output current i os address 50 50 ma recommended operating conditions (voltage referenced to vss, t a = 0 to 70 c) *1 : v cc +1.3v/15ns(3.3v), v cc +2.0v/20ns(5v), pulse width is measured at v cc *2 : -1.3v/15ns(3.3v), -2.0v/20ns(5v), pulse width is measured at v ss parameter symbol 3.3v 5v units min typ max min typ max supply voltage v cc 3.0 3.3 3.6 4.5 5.0 5.5 v ground v ss 0 0 0 0 0 0 v input high voltage v ih 2.0 - v cc +0.3 *1 2.4 - v cc +1.0 *1 v input low voltage v il -0.3 *2 - 0.8 -1.0 *2 - 0.8 v dc and operating characteristics (recommended operating conditions unless otherwise noted.) max parameter symbol min max units 3.3v input leakage current (any input 0 v in v in +0.3v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-2ma) v oh 2.4 - v output low voltage level(i ol =2ma) v ol - 0.4 v 5v input leakage current (any input 0 v in v in +0.5v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-5ma) v oh 2.4 - v output low voltage level(i ol =4.2ma) v ol - 0.4 v
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c *note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 , i cc3 and i cc6 address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one fast page mode cycle time, t pc . dc and operating characteristics (continued) i cc1 * : operating current ( ras and cas , address cycling @t rc =min.) i cc2 : standby current ( ras = cas = w =v ih ) i cc3 * : ras -only refresh current ( cas =v ih , ras , address cycling @t rc =min.) i cc4 * : fast page mode current ( ras =v il , cas , address cycling @t pc =min.) i cc5 : standby current ( ras = cas = w =v cc -0.2v) i cc6 * : cas -before- ras refresh current ( ras and cas cycling @t rc =min.) i cc7 : battery back-up current, average power supply current, battery back-up mode input high voltage(v ih )=v cc -0.2v, input low voltage(v il )=0.2v, cas =0.2v, dq=don t care, t rc =31.25us(4k/l-ver), 62.5us(2k/l-ver), t ras =t ras min~300ns i ccs : self refresh current ras = cas =0.2v, w = oe =a0 ~ a11=v cc -0.2v or 0.2v, dq0 ~ dq3=v cc -0.2v, 0.2v or open symbol power speed max units k4f170412c k4f160412c k4f170411c k4f160411c i cc1 don t care -50 -60 90 80 110 100 90 80 110 100 ma ma i cc2 normal l don t care 1 1 1 1 2 1 2 1 ma ma i cc3 don t care -50 -60 90 80 110 100 90 80 110 100 ma ma i cc4 don t care -50 -60 80 70 90 80 80 70 90 80 ma ma i cc5 normal l don t care 0.5 200 0.5 200 1 250 1 250 ma ua i cc6 don t care -50 -60 90 80 110 100 90 80 110 100 ma ma i cc7 l don t care 250 250 300 300 ua i ccs l don t care 200 200 250 250 ua
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c capacitance (t a =25 c, v cc =5v or 3.3v, f=1mhz) parameter symbol min max units input capacitance [a0 ~ a11] c in1 - 5 pf input capacitance [ ras , cas , w , oe ] c in2 - 7 pf output capacitance [dq0 - dq3] c dq - 7 pf test condition (5v device) : v cc =5.0v 10%, vih/vil=2.4/0.8v, voh/vol=2.4/0.4v parameter symbol -50 -60 units notes min max min max random read or write cycle time t rc 90 110 ns read-modify-write cycle time t rwc 133 155 ns access time from ras t rac 50 60 ns 3,4,10 access time from cas t cac 13 15 ns 3,4,5 access time from column address t aa 25 30 ns 3,10 cas to output in low-z t clz 0 0 ns 3 output buffer turn-off delay t off 0 13 0 15 ns 6 transition time (rise and fall) t t 3 50 3 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 13 15 ns cas hold time t csh 50 60 ns cas pulse width t cas 13 10k 15 10k ns ras to cas delay time t rcd 20 37 20 45 ns 4 ras to column address delay time t rad 15 25 15 30 ns 10 cas to ras precharge time t crp 5 5 ns row address set-up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set-up time t asc 0 0 ns column address hold time t cah 10 10 ns column address to ras lead time t ral 25 30 ns read command set-up time t rcs 0 0 ns read command hold time referenced to cas t rch 0 0 ns 8 read command hold time referenced to ras t rrh 0 0 ns 8 write command hold time t wch 10 10 ns write command pulse width t wp 10 10 ns write command to ras lead time t rwl 13 15 ns write command to cas lead time t cwl 13 15 ns ac characteristics (0 c t a 70 c, see note 1,2) test condition (3.3v device) : v cc =3.3v 0.3v, vih/vil=2.0/0.8v, voh/vol=2.0/0.8v
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c ac characteristics (continued) parameter symbol -50 -60 units note min max min max data set-up time t ds 0 0 ns 9 data hold time t dh 10 10 ns 9 refresh period (2k, normal) t ref 32 32 ms refresh period (4k, normal) t ref 64 64 ms refresh period (l-ver) t ref 128 128 ms write command set-up time t wcs 0 0 ns 7 cas to w delay time t cwd 36 40 ns 7 ras to w delay time t rwd 73 85 ns 7 column address to w delay time t awd 48 55 ns 7 cas precharge to w delay time t cpwd 53 60 ns cas set-up time ( cas -before- ras refresh) t csr 5 5 ns cas hold time ( cas -before- ras refresh) t chr 10 10 ns ras to cas precharge time t rpc 5 5 ns access time from cas precharge t cpa 30 35 ns 3 fast page cycle time t pc 35 40 ns fast page read-modify-write cycle time t prwc 76 85 ns cas precharge time (fast page cycle) t cp 10 10 ns ras pulse width (fast page cycle) t rasp 50 200k 60 200k ns ras hold time from cas precharge t rhcp 30 35 ns oe access time t oea 13 15 ns oe to data delay t oed 13 15 ns output buffer turn off delay time from oe t oez 0 13 0 15 ns 6 oe command hold time t oeh 13 15 ns write command set-up time (test mode in) t wts 10 10 ns 11 write command hold time (test mode in) t wth 10 10 ns 11 w to ras precharge time( c -b- r refresh) t wrp 10 10 ns w to ras hold time( c -b- r refresh) t wrh 10 10 ns ras pulse width ( c -b- r self refresh) t rass 100 100 us 13,14,15 ras precharge time ( c -b- r self refresh) t rps 90 110 ns 13,14,15 cas hold time ( c -b- r self refresh) t chs -50 -50 ns 13,14,15
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c test mode cycle parameter symbol -50 -60 units notes min max min max random read or write cycle time t rc 95 115 ns read-modify-write cycle time t rwc 138 160 ns access time from ras t rac 55 65 ns 3,4,10,12 access time from cas t cac 18 20 ns 3,4,5,12 access time from column address t aa 30 35 ns 3,10,12 ras pulse width t ras 55 10k 65 10k ns cas pulse width t cas 18 10k 20 10k ns ras hold time t rsh 18 20 ns cas hold time t csh 55 65 ns column address to ras lead time t ral 30 35 ns cas to w delay time t cwd 41 45 ns 7 ras to w delay time t rwd 78 90 ns 7 column address to w delay time t awd 53 60 ns 7 cas precharge to w delay time t cpwd 58 65 ns fast page cycle time t pc 40 45 ns fast page read-modify-write cycle time t prwc 81 90 ns ras pulse width (fast page cycle) t rasp 55 200k 65 200k ns access time from cas precharge t cpa 35 40 ns 3 oe access time t oea 18 20 ns oe to data delay t oed 18 20 ns oe command hold time t oeh 18 20 ns ( note 11 )
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c notes an initial pause of 200us is required after power-up followed by any 8 ras -only refresh or cas -before- ras refresh cycles before proper device operation is achieved. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 5ns for all inputs. measured with a load equivalent to 2 ttl(5v)/1 ttl(3.3v) loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). t off (min)and t oez (max) define the time at which the output achieves the open circuit condition and are not referenced v oh or v ol . t wcs , t rwd , t cwd and t awd are non restrictive operating parameters. they are included in the data sheet as electrical charac- teristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain high impedance for the dura- tion of the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min) and t awd 3 t awd (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to cas falling edge in early write cycles and to w falling edge in read-modify-write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . these specifications are applied in the test mode. in test mode read cycle, the value of t rac , t aa , t cac is delayed by 2ns to 5ns for the specified values. these parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. if t rass 3 100us, then ras precharge time must use t rps instead of t rp . for ras -only refresh and burst cas -before- ras refresh mode, 4096(4k)/2048(2k) cycles of burst refresh must be exe- cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification. for distributed cas -before- ras with 15.6us interval cas -before- ras refresh should be executed with in 15.6us immedi- ately before and after self refresh in order to meet refresh specification. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 1. 2. 3. 4. 15.
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c t crp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq3(7) read cycle column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t aa t oea t cac t clz t rac open data-out t oez t rrh t rch don t care undefined t rcs t off
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c t wcs write cycle ( early write ) note : d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t wp t ds t dh t wch t cwl t rwl don t care data-in undefined
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c t oed ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp data-in t wp don t care write cycle ( oe controlled write ) note : d out = open t cwl t rwl t ds t dh t oeh undefined
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq3(7) row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp valid t wp don t care read - modify - wrtie cycle t rwl t cwl t oez t oea t oed t awd t cwd t rwd data-out undefined valid data-in t rac t aa t cac t clz t ds t dh column address
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c t rch t oez t clz ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq3(7) column address row addr t rhcp t rasp t cas t asc t rad t asr t rah t asc t cah t crp valid don t care fast page read cycle t oez t rrh data-out undefined valid data-out column address column address t rsh t cas t rcd t pc ? t csh t cah t asc t cah ? ? ? t rch ? t rcs t rcs t rcs t oea t cac t oea t cac t oea t cac valid data-out t clz t off t aa t off t aa t clz t off t oez t rac t aa ? ? t cp t cas t rp t cp t ral
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c t asc t cah ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row addr t rhcp t rasp t cas t rad t asr t rah t asc t crp valid don t care fast page write cycle ( early write ) data-in undefined valid data-in t ds note : d out = open column address column address t rsh t cas t rcd t pc ? t csh t cah t cah ? ? ? t wcs t wch t wcs valid data-in ? ? t wp t cwl t wp t wch t wp t wcs t wch t cwl t rwl t cwl t dh t ds t dh t ds t dh ? ? ? t rp t cp t cp t cas t pc t ral t asc
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c t cac t asc t asc ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq3(7) row addr t csh t rasp t asr valid don t care fast page read - modify - write cycle data-out undefined t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t cah t ral t prwc t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t aa t rac t oea t clz t cac t oez t cpwd t oed valid data-in valid data-out valid data-in t clz t ds t oea t aa t dh t ds t oez t oed t rwl t rp t rsh t rah
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t ras t rc t rp t asr t rah t crp don t care ras - only refresh cycle undefined note : w , oe , d in = don t care d out = open t rpc t crp cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t ras t rc t rp t wrp t rpc t rp t cp t chr t csr w v ih - v il - t wrh t off t rpc v oh - v ol - dq0 ~ dq3(7) open
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c t wrh t off ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq3(7) hidden refresh cycle ( read ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp t rcs t aa t oea t cac t clz t rac open don t care t rsh t oez undefined t rc data-out t rp t rp t ras t ral
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) hidden refresh cycle ( write ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp don t care t rsh data-in t wrp t wrh undefined t rc note : d out = open t wch t wp t dh t rp t rp t ras t ds t wcs t ral
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c don t care undefined cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rass t rps t rpc t wrp t chs t rp t cp t csr w v ih - v il - t wrh t off t rpc open v oh - v ol - dq0 ~ dq3(7) test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t ras t rc t rp t rpc t wts t rpc t rp t cp t chr t csr w v ih - v il - t wth t off open v oh - v ol - dq0 ~ dq3(7)
k4f170411c, k4f160411c cmos dram k4f170412c, k4f160412c 0 . 3 0 0 ( 7 . 6 2 ) 0 . 3 3 0 ( 8 . 3 9 ) 0 . 3 4 0 ( 8 . 6 3 ) 0.680 (17.28) 0.670 (17.03) max 0.691 (17.55) m a x 0 . 1 4 8 ( 3 . 7 6 ) 0.0375 (0.95) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.015 (0.38) 0.027 (0.69) 0.012 (0.30) 0.006 (0.15) 0 . 2 6 0 ( 6 . 6 1 ) 0 . 2 8 0 ( 7 . 1 1 ) min #26(24) 0.050 (1.27) 26(24) soj 300mil units : inches (millimeters) package dimension 26(24) tsop(ii) 300mil max 0.047 (1.20) min 0.002 (0.05) 0.020 (0.50) 0.012 (0.30) 0.050 (1.27) 0.037 (0.95) 0.671 (17.04) 0.679 (17.24) 0.691 (17.54) max 0.010 (0.25) 0.004 (0.10) 0 . 3 0 0 ( 7 . 6 2 ) 0 . 3 7 1 ( 9 . 4 2 ) 0 . 3 5 5 ( 9 . 0 2 ) units : inches (millimeters) 0~8 0.030 (0.75) 0.018 (0.45) typ 0.010 (0.25) o

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